This book constitutes the refereed proceedings of the 10th Internation al Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Goettingen, Germany in September 2000. The 33 re vised full papers presented were carefully reviewed and selected for i nclusion in the book. The papers are organized in sections on RTL powe r modeling, power estimation and optimization, system-level design, tr ansistor level design, asynchronous circuit design, power efficient te chnologies, design of multimedia processing applications, adiabatic de sign and arithmetic modules, and analog-digital circuit modeling.